LVS DEBUG SOLUTIONS LLC

Services offered:

• FullChip LVS/DRC Debug Through Tapeout
• Perl/Shell Based FullChip Netlist Parsing, Circuit Tree Extraction from Spice
• Calibre SVRF/TVF Based Decks Development
• CalibreDRV TCL, Calibre SVRF To Edit GDS Data
• CalibreDRV TCL, Shell, SVRF, Perl Based Fab-To-Fab GDS Data Conversion
• AtopTech DRC/LVS Fixing, Shell/Perl Based PrimeTime Report Parsing
• Shell/Perl Based Calibre Flow Development
• LatchUp, ERC, SurgePath Analysis In Multi-Voltage Domains Designs
• Spice Simulations
• Power shutdown domains analysis
• CalibreDRV macros tcl/tk
• Digital/Aanalog  circuit IPs, Piston/Pawl IPs, Green tech components including multi-AC

LLC STATUS AS OF Nov 01, 2018

 To check for latest status, please  visit  https://businesssearch.sos.ca.gov/ 

click "Search by LP/LLC name" button, type "LVS DEBUG SOLUTIONS LLC"  in Search Criteria, press "Search".

In the next window, clicking on Entity Name shows details, including statements of information.



LVS DEBUG SOLUTIONS LLC open in July 2019 for LVS Debug and/or creating a Center for Innovations and Early Developments on the IPs (early communications welcome)

... Typically go to client site and work. Additional work done over vpn. Can work on projects outside of bay area also, as well as in overseas locations.

Requested Rate: $100/hour. negotiable for larger contracts

High Per Capita Creative Output (PCCO)

Don't cheat your shareholders/customers - they are thinking you are getting work done by the best and the brightest!

Call the workhorse Today!

Proprietor/single member:

Arya Raychaudhuri*

(*profile on www.linkedin.com, full  resume on backpage of this website)

New features: Transverse Moore's Law driving JK FlipFlop (see 'code snippets3' page, Item#s 363, 364)

Notes:

Physical verification, extraction, IR drop, design migration project with Jasper Display Corporation : Feb 4, 2019 -

Chip surgery with Calibre, project with Avago/Broadcom - November 13, 2018 - Jan 30, 2019

April 5, 2018 - Four years in a row, Santa Clara business award for consulting services:

Did 200+ code snippets for LVS DEBUG SOLUTIONS LLC between Sept 2016 and March 2018 (see code snippets2, code snippets3 and code snippets4 pages)



March 8, 2017 - Three years in a row, Santa Clara business award for consulting services

Santa Clara Business Hall of Famer, 2016 - July 29, 2016

Finished  a multi-chip module PV --> Tapeout  for Avago/Broadcom (now an approved consulting vendor for Broadcom) - March 2016 - July 2016

Helped Eximius Design LLC with a 28nm Design tapeout (ICV + Calibre) - December 2015 - Feb 2016

Consulting Services awardee, 2015

Arya Raychaudhuri

-Sept 30, 2015

Member ACM by invitation

- Sept 2015 (Renewed 29 Sept 2017)

CAD engg contractor at Intel (through Aditi Staffing) -

May 2015 --- Nov 2015

Attended Mentor Graphics U2U conference in San Jose - April 2015

Completed 206 snippets on the 'code snippets' page. exhibits high per capita creative output (PCCO) - March 2015

Donates to Wikipedia and Mozilla for their usefulness,  December 2014

Gives up Sole Proprietor entity LVS DEBUG SOLUTIONS, only retains the LLC entity LVS DEBUG SOLUTIONS LLC - December 2014

Home Office moved to Santa Clara, California - 980 Kiely Blvd, Unit 308 Santa Clara, CA 95051 - June 2014 [Updated LLC status included below]

"Arya Raychaudhuri did a very good job to help our team at PLX with Physical Verification (DRC/LVS) and resulted in a successful tape-out of a very complex multi-chip module"

- Duc Vu,

Physical Design Manager                            PLX Technology                    (now part of Avago)

Single-handedly executes the physical verification of the multiChip towards PLX's ExpressFabric - June 2014

LVS DEBUG SOLUTIONS LLC Contact Information Change - see top right corner, also, the original sole proprietorship - LVS DEBUG SOLUTIONS will share the same contact address.

LVS DEBUG SOLUTIONS sees 82% upswing in 2013 business over 2012 ...

Helping PLX Technology on physical verification of a multi-chip module... Done

(July2013 - May2014)

"Arya has worked on multiple chips in parallel for a very condensed period of time being responsible of physical verification in particular LVS. He successfully completed LVS for two complex 40nm  chips, which included power domains, multiple IP’s from various vendors, one flip-chip and one wire-bond. Both chips returned and no issues were reported"

- Jack Feldman

Director, eSilicon, July10, 2013

Helped PLX technology on a small ECO on a multiChip module...Done

(April 2013 -- June 2013)

"Arya has been instrumental in completing LVS for a complex 40nm flip-chip design containing several complex IP macros from multiple vendors."

-Rakesh Chadha

Director, eSilicon

(Feb23, 2013)

Helped eSilicon with physical design verification, first tapeout-worthy LVS debug in early Jan 2013, second (28nm) tapeout Feb 2013, third tapeout (40nm) early April 2013, fourth (40nm) May 2013, multiple ECOs...

(Oct 2012 - Dec 2013 ) 

Emergency LVS debug for koolchip

(Oct 2012)

LVS DEBUG SOLUTIONS starts the Blog page

(Oct 2012)

Canopy connection based short detection (done)

(July 2012)

LVS DEBUG SOLUTIONS starts the Code Snippets page

(July 2012)

Customer Comments on workhorse Arya:

- Syed Ahmed

Sr. Director, Physical Design

(Date: July 12, 2012)

LVS DEBUG SOLUTIONS becomes California LLC (entity#201212410242)

(Apr 24, 2012)

LVS DEBUG SOLUTIONS helps Jasper Display with Calibre SVRF based Via density correction - Done

(May 2012)

LVS DEBUG SOLUTIONS solves the LVS puzzle for a multi-chip module ... working on another metals respin tapeout for PLX - Completed!

(June 2012)

LVS DEBUG SOLUTIONS completes first project on hspice based static and dynamic leakage power analysis for PLX Technology!

(Dec 2011)